ECE 171: Introduction to Digital Circuits

 Fall 1999

Rev: 9.30.99

Design Project 3

Problem Description

Continuing with Project 1 and 2, you will now implement the design in a PAL (programmable array logic device). Again, A large part of the grade for this project is based on how thoroughly and clearly you document your work.

To Complete the Project

  1. Do the WARP tutorial to learn how to make a .jed file for a VHDL design and how to simulate the .jed file.
  2. Write a rough draft of a VHDL file for your six variable design using the equations derived from your K-maps.
  3. Invoke Galaxy and create a .vhd file as you did in the tutorial. After carefully checking the file, save it as sixvar.vhd. Add comments to the final to explain what the code is doing.
  4. Add sixvar.vhd to the Warp2 Input File list, go to the Options form and choose C16v8, then Compile and Synthesize the design.
  5. If there are syntax errors, edit the .vhd file to correct them, then repeat the Compile and Synthesize. If there are no syntax errors, invoke the Nova simulator.
  6. In Nova, open the sixvar.jed file, generate the stimulus signals, and simulate the circuit as described in the tutorial.
  7. Use your original truth table to determine if the outputs are correct.
  8. If all values are correct, write vectors to the .jed file and write the trace (.psd) file.
  9. Exit from Galaxy.
  10. Print copies of your .vhd, .rpt and .psd files (you could use "enscript" for this printout).

Final Report

The report for this project will be less formal than the previous two projects. The report must be typed and include the following sections.

I do hereby affirm that I designed this circuit by myself.

Signed __________________________________

Date _______________

Grading

Project 3 is worth 10 points of 50 total project points.