Book uses a symbol that is inconsistent
T Flip Flop
Toggles every clock
Is also called a frequency divider
because the output waveform has half the frequency of the input
Can be combined with an enable
Ripple Counters & Frequency
Draw three bit ripple counter
with T Flip Flops (falling edge triggered)
Draw waveforms and show that
it counts from 0 to 7 and then starts over at 0 again
This is also thought of as a
frequency divider because the output waveforms have a frequency
that is some power of 2 times less than the clock signal driving
The ripple counters can only
divide by powers of 2
You can build a ripple counter
that is of any modulo (number of different output states) by
resetting the flip flops when you reach the final state.
Show how a three bit modulo-8
ripple counter can be converted into a modulo-6 ripple counter.
Recall Gate's Room Illumination
System that we discussed earlier in the quarter
There were two doors that people
could enter from, door A and door B, and one exit, door E. Each
of these is connected to a sensor that produces a 1 when the
door is open and a 0 when the door is closed.
Earlier in the quarter we were
only able to turn the lights on when either A or B was high,
which was acheived with a simple OR gate.
Now we can turn the lights off
as well. Suppose the output of our system, L, controls whether
the lights are on (1) or off (0).
There are many ways to solve
theis problem. The one we will use is to use two counters: one
to count the number of entries and one to count the number of
exits. If they're both the same, then the room is empty and we
can turn the lights out.
Draw two counters.
How big should the counters
be? What is the room capacity? If 30, then we need a modulo-32
counter, which has 5 outputs.
We need some method of determining
whether the outputs are the same. We can do this bit by bit with
an exclusive NOR.
We need some method of combining
all of the comparators. This can be done by a single AND gate.
But we want the output L to be low when the counters are equal,
so we should use a 5-input NAND gate.
The input to the exits counter
should be the door E signal.
But we have two signals for
the entries: A and B. How should we combine them to produce a
single clock signal?
Draw possible input waveforms
with a set of overlapping pulses on the A input and B input.
If we use an OR gate, the clock
signal will miss it when door A and B are opened at the same
If we use an XOR gate, it will
count all of the entries, even when the pulses are overlapping
or of different sizes.
However, this won't catch the
problem if the pulses are at exactly the same time. But this
would be unlikely to occur, especially since they would have
to be within nanoseconds of one another for our logic to miss
The book describes other applications
Ripple Counter Glitches &
Draw first 5 or 6 clock pulse
outputs of a three bit ripple counter.
Show that the delays increase
as the counter becomes larger (delay).
Show that there are some
intermediate states that are completely wrong (glitch).
These are the problems of
using ripple counters.
Synchronous counters avoid the
delays and glitches of ripple counters because all of the flip
flops change at the same time.
Draw the architecture of
a three-bit synchronous counter using D flip flops.
When the clock edge occurs,
all three flip flops change simultaneously.
The propagation delay is the
same regardless of the size of the counter.
The propagation delay is also
relatively small: the same as for a single flip flop.
This eliminates glitches.
Combinational logic is used
to decode the next state before the next clock edge occurs.
Synchronous Counter Design w/
D Flip Flops
Fill out the truth table
for a 3-bit synchronous counter with D flip flops.
Most of the expressions can
be obtained by observation directly from the truth table.
A+ = A'
B+ = A XOR B
C is more difficult and can
be obtained from a Karnaugh map.
C+ = C'AB + CB' + CA'
= C'(AB) + C(A' + B')
= C'(AB) + C(AB)'
= C XOR (AB)
Draw logic diagram
Synchronous Counters w/T Flip
This type of design is much
Draw truth table
Each variable only toggles when
all of the less significant bits are 1.
Draw logic diagram.
For each bit you can use the
outputs of the preceding AND gates, so you only need a 2-input
AND gate for each additional stage.