ECE 171: Introduction to Digital Circuits

Fall 1999

Rev: 11.16.99

Lecture Notes 14

Last Time

• BCD7-Segment Displays
• PLD's
  • Overview
  • PLA's - Won't discuss because obsolete
  • PROM's
  • PAL Devices
• Static-1/0 Hazards
• Gray Code

This Time

• Latches & Flip Flops
  • SR Latch
  • S'R' Latch
  • D Latch
  • D Flip Flop
  • Enables
  • Presets & Clears
• Exam 2 Topics & Review

Latches & Flip FLops

• Latches and Flip Flops are used as temporary memories
• Each stores a single (important) bit
• You can think of them as bit storage devices
• Distinction
  • Flip flops only change on the edge of a clock signal. The change may occur on the rising edge or on the falling edge. Since they only change with the clock signal these devices are said to be synchronous.
  • Latches do not depend on a clock signal and are said to be asynchronous.
• These devices are essential to counters and state machines which you will discuss in ECE271.
• Both devices are constructed from the 8 basic logic gates we've discussed in class.
• However, flip flops and latches are also fundamental devices that are used extensively in most IC's including counters, microprocessors, programmable gate arrays, etc.

SR Latch

• This is the most fundamental
  • Draw diagram using NOR gates.
  • S is a mnemonic for set and R is a mnemonic for reset.
  • Truth table
    

    S	R	Q	Qn
    0	0	Q*	Qn*
    0	1	0	1
    1	0	1	0
    1	1	0	0

  • This last state is usually prohibited or declared illegal because if both inputs change from 11 to 00 the output is undefined.
  • In many books Q' (Q-bar) is used instead of Qn. I've used Qn because in the prohibited state Qn is not equal to the complement of Q.
  • The asterisk (*) denotes the previous state. Thus, when SR=00, the latch remembers or stores the last set of outputs that it had.
  • IDraw symbols. Show the wrong way to draw the symbol with the complemented output labled Qn' and a bubble.
  • One of the specifications listed in data sheets for these devices is the minimal pulse width to set and reset the device. If SR=10 very briefly, the device may not be set as requested.

Application

• Draw a debouncing circuit with the pole tied to +5V and the S & R inputs to the SR latch pulled low by pull-down resistors.
• When the switch is not making contact (open circuit) the pull down resistors set SR=00 and the device remebers the last state it was in.
• Thus, if the switch bounces on the contact several times before permanently setting it high, the output of the latch will keep a steady high output.
• Illustrate this idea with a timing diagram.

S'R' Latch

• Draw the logic diagram for an S'R' latch using NAND gates.
• Draw the preferred symbol.
• Truth table
  

  S'	R'	Q	Qn
  0	0	1	1
  0	1	1	0
  1	0	0	1
  1	1	Q*	Qn*

• The first entry in the truth table is the illegal or prohibited state.

SR Latch with Enable

• Draw diagram with S'R' latch and two additional NAND gates to show how an enable can be added to this device.
• Draw the preferred symbol.
• Truth Table
  

  C	S	R	Si'	Ri'	Q	Qn
  0	X	X	1	1	Q*	Qn*
  1	0	0	1	1	Q*	Qn*
  1	0	1	1	0	0	1
  1	1	0	0	1	1	0
  1	1	1	0	0	1	1

D Latch with Enable

• Draw diagram using the SR latch with enable this time and a single inverter.
• Draw preferred symbol.
• Truth Table
  

  C	D	Q	Q'
  0	X	Q*	Q'*
  1	0	0	1
  1	1	1	0

• Note that SR is never 11, so the prohibited state never occurs with this device.
• Consequently I used Q' instead of Qn because Q' is always equal to the complement of Q.
• When the device is enabled Q is just equal to D. When the device is disabled it remembers it's previous state.

D Flip Flop

• Draw diagram using two D latches with enable and a clock signal routed through two inverters.
• Explain how the device works by use of a timing diagram that contains the D input, the clock signal, the output of the internal latch, and the output of the final latch.
• Draw the truth table and introduce the uparrow, a new symbol for truth tables.
• Draw the preferred symbol.

D Flip Flop with Preset & Clear

• Draw the preferred symbol.
• Explain that the PRE input sets the latch asynchronously (does not have to wait for a clock edge).
• The CLR input resets the latch asynchronously.
• It is a bad idea to try to both set and reset the device simultaneously so this is normally avoided by design (much like the prohibited states discussed earlier).
• Go over truth table for 74AC11074
  • An entry was left off the truth table when the CLK is high and PRE' and CLR' are both high. This should have been the same as the last row in the table.
  • This device contains two identical D flip flops with two separate clock inputs.
  • Note that PRE and CLR inputs are active low.
  • Read note on what happens when both PRE' and CLR' inputs are asserted.

Exam 2 Review

Go over what is listed in the Exam 2 Topics and answer any general questions that students have.
Review static hazards and note that they are discussed in the beginning of chapter 8.