OpenRISC System-on-Chip Design Emulation

Executive Statement

New computer systems like smart phones and tablets, are entering the market at an ever-accelerating pace. This brings enormous pressure on the product development teams to shorten the time-to-market. Driven by increasing design complexity and decreasing time-to-market, it demands innovative approaches to accelerating hardware design simulation, verification, and debugging.

Recently the hardware emulation technique has emerged as a promising approach to accelerating hardware verification/debugging process. This project aims to fully demonstrate the benefits of hardware emulation for accelerating hardware design verification and testing. In this project, we carry out the following tasks with Mentor Graphics Veloce:

  1. standalone emulation of  an existing open-source SoC design, OpenRISC Reference Platform System on Chip (ORPSoC);
  2. emulation performance evaluation with three categories of benchmarks over ORPSoC, booting the Linux kernel, running CHStone benchmark, and
    running ‘simple sum N’ program;
  3. thoroughly comparison with the simulation approach: simulating ORPSoC with the benchmarks on Mentor Graphics QuestaSim.

Project Members