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The design of a VLSI system is unthinkable
without the use of numerous computer-aided design
(CAD) tools, which automate most design tasks.
Except for the initial specification of the system,
every other step of the design process has been
either automated simplified through user-friendly
CAD tools/programs. There are three general aspects
of CAD: (1) synthesis, (2) verification, and (3)
design management. The sequence of these two
classes focuses on the synthesis aspect of the
design process and more specifically on physical
synthesis (layout synthesis) : partitioning,
floorplanning, placement, and routing.
Improvements in semiconductor processing create
an ever widening frontier of challenges for
electronic design automation. Performance
improvement of ULSI IC's fabricated in deep
sub-micron technology depends very strongly on the
delay of interconnects. For the current leading
technologies with active-device count reaching the
tens of millions, the delay of interconnects is
responsible for about 40-50 % of the total delay
associated with a circuit and this contribution is
predicted to increase
Therefore, the problems of predicting the
interconnect contribution to delay, power, area,
and noise during the optimization steps, and
handling the signal integrity problem became the
major bottle neck of the synthesis process. As a
result, the physical synthesis approaches have to
be reexamined and new solutions need to be found. A
large number of CAD specialists is necessary to
develop these new solutions and tools for physical
design automation.
In this sequence we start with an overview of
the physical design automaton field and discuss the
fabrication process for VLSI devices. Scaling and
deep-submicron issues relevant to physical design
automation are introduced as well. Subsequently, we
review the necessary background in graph theory and
combinatorial optimization techniques needed to
understand the algorithms and optimization methods
used in physical design automation. Next, specific
sub-problems in IC layout, starting with circuit
partitioning, are discussed. Algorithms for
floorplanning, placement, and global and detailed
routing with timing constraints are analyzed in
details. Specialized algorithms for designing with
FPGAs are introduced. We also discuss integration
between logic and layout synthesis which is
becoming increasingly important for deep-submicron
technologies.
Target students:
CAD tool developers working on design automation
approaches in physical layout and in logic
synthesis. People with computer science or math
backgrounds who want to move to the design
automation field. This class is also relevant to
VLSI designers using CAD tools.
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