RISC-V
An Overview of the Instruction Set Architecture
The RISC-V project defines and describes a standardized Instruction Set Architecture (ISA). RISC-V is an open-source specification for computer processor architectures, not a particular chip or implementation. To date, several different groups have designed and fabricated silicon implementations of the RISC-V specifications. Based on the performance of these implementations and the growing need for interoperability among vendors, it appears that the RISC-V standard will increase in importance.
This document introduces and explains the RISC-V standard, giving an informal overview of the architecture of a RISC-V processor. This document does not discuss a particular implementation; instead we discuss some of the various design options that are included in the formal RISC-V specification.
This document gives the reader an initial introduction to the RISC-V design.
About the Author
Harry H. Porter III, Ph.D.
Computer Science Department
Portland State University
Short Bio:
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Harry's Website: www.cs.pdx.edu/~harry
Email: hhporter3@gmail.com