
     | | | | | | |
   _________________
  -|               |-
  -|               |-
  -|               |-
  -|    CYPRESS    |-
  -|               |-
  -|               |-   Warp VHDL Synthesis Compiler: Version 4 IR x66
  -|               |-   Copyright (C) 1991, 1992, 1993,
   |_______________|                  1994, 1995, 1996 Cypress Semiconductor
     | | | | | | |

======================================================================
Compiling:  fsm.vhd
Options:    -dc22v10 -pPALC22v10-20HC fsm.vhd
======================================================================

vhdlfe V4 IR x66:  VHDL parser
Wed Mar  7 15:58:54 2001

Library 'work' => directory 'lc22v10'

vhdlfe:  No errors.


tovif V4 IR x66:  High-level synthesis
Wed Mar  7 15:58:54 2001


tovif:  No errors.


topld V4 IR x66:  Synthesis and optimization
Wed Mar  7 15:58:55 2001

State variable 'state' is represented by a Bit_vector (0 to 0).
State encoding (sequential) for 'state' is:
	a :=	b"0";
	b :=	b"1";

----------------------------------------------------------
Detecting unused logic.
----------------------------------------------------------



------------------------------------------------------
Alias Detection
------------------------------------------------------

------------------------------------------------------
Aliased 0 equations, 1 wires.
------------------------------------------------------

----------------------------------------------------------
Circuit simplification
----------------------------------------------------------

----------------------------------------------------------
Circuit simplification results:

	Expanded 0 signals.
	Turned 0 signals into soft nodes.
	Maximum expansion cost was set at 10.
----------------------------------------------------------
Created 7 PLD nodes.

topld:  No errors.

----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    17/JUL/96    [v3.22 ] 4 IR x66

DESIGN HEADER INFORMATION  (15:58:55)

Input File(s): fsm.pla
Device       : C22V10
Package      : PALC22v10-20HC
ReportFile   : fsm.rpt

Program Controls:
                 None.

Signal Requests:
                 None.

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    17/JUL/96    [v3.22 ] 4 IR x66

OPTIMIZATION OPTIONS       (15:58:55)

Messages:
  Information: Process virtual 'stateSBV_0D' ... expanded.
  Information: Selected logic optimization OFF for signals:
         q.D q.C qbar



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Optimizer Software:       MINOPT.EXE     17/JUL/96    [v3.22 ] 4 IR x66

LOGIC MINIMIZATION         (15:58:55)

Messages:


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software:       DSGNOPT.EXE    17/JUL/96    [v3.22 ] 4 IR x66

OPTIMIZATION OPTIONS       (15:58:55)

Messages:
  Information: Optimizing Banked Preset/Reset requirements.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

DESIGN EQUATIONS           (15:58:56)


    qbar =
          /q.Q 

    q.D =
          clear * serdata 

    q.AR =
          GND

    q.SP =
          GND

    q.C =
          clk 


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

DESIGN RULE CHECK          (15:58:56)

Messages:
                 None.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

DESIGN SIGNAL PLACEMENT    (15:58:56)

Messages:
  Information: Checking for duplicate NODE logic.
                 None.

                    Device:  C22V10
                    Package: PALC22v10-20HC

                         s                
                         e              u 
                      c  r              n 
                      l  d           q  u 
                      e  a  c     V  b  s 
                      a  t  l  N  C  a  e 
                      r  a  k  C  C  r  d 
                      |  |  |  |  |  |  | 
                    ________________________
                    | 4  3  2  1  28 27 26 |
                    |                      |
             unused_| 5                  25|_unused        
             unused_| 6                  24|_unused        
             unused_| 7                  23|_unused        
                 NC_| 8                  22|_NC            
             unused_| 9                  21|_unused        
             unused_|10                  20|_unused        
             unused_|11                  19|_unused        
                    |                      |
                    | 12 13 14 15 16 17 18 |
                    ________________________
                      |  |  |  |  |  |  | 
                      u  u  G  N  u  q  u 
                      n  n  N  C  n     n 
                      u  u  D     u     u 
                      s  s        s     s 
                      e  e        e     e 
                      d  d        d     d 



Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

RESOURCE ALLOCATION        (15:58:56)

  Information: Macrocell Utilization.

                     Description        Used     Max
                 ______________________________________
                 | Dedicated Inputs   |    2  |   11  |
                 | Clock/Inputs       |    1  |    1  |
                 | I/O Macrocells     |    2  |   10  |
                 ______________________________________
                                           5  /   22   = 22  %


  Information: Output Logic Product Term Utilization.

                  Node#  Output Signal Name  Used   Max
                 ________________________________________
                 | 14  |  q               |   1  |   8  |
                 | 15  |  Unused          |   0  |  10  |
                 | 16  |  Unused          |   0  |  12  |
                 | 17  |  Unused          |   0  |  14  |
                 | 18  |  Unused          |   0  |  16  |
                 | 19  |  Unused          |   0  |  16  |
                 | 20  |  Unused          |   0  |  14  |
                 | 21  |  Unused          |   0  |  12  |
                 | 22  |  Unused          |   0  |  10  |
                 | 23  |  qbar            |   1  |   8  |
                 | 25  |  Unused          |   0  |   1  |
                 ________________________________________
                                              2  / 121   = 1   %


Completed Successfully  
----------------------------------------------------------------------------
PLD Compiler Software:        PLA2JED.EXE    17/JUL/96    [v3.22 ] 4 IR x66

JEDEC ASSEMBLE             (15:58:56)

Messages:
  Information: Output file 'fsm.jed' created.


Summary:
                 Error Count = 0      Warning Count = 0

Completed Successfully at 15:58:56
