Evolvable hardware (EHW) combines the power of evolutionary computation with the flexibility of reconfigurable devices such as field programmable gate arrays (FPGA), field programmable analog arrays (FPAA) or field programmable transistor arrays (FPTA).

At the Evolvable Systems Laboratory (ESL) our objective is to study adaptive systems and to develop new ways to make circuitry and system adapt to compensate for faults or to accommodate changing operational environments.

One investigation involves adapting circuitry to continue operating at elevated temperatures. The basic testbench used in our lab is shown below:

Figure 1: Temperature testing testbench. The reconfigurable circuitry is an FPAA.

Another investigation is the study of evolving circuit topology. This work uses an Evolvable Analog Research Platform(EARP-1). Figure 2 shows the logical organization of EARP-1. The EARP-1 mainframe chassis provides a set of 16 analog bus lines, which are used to carry input signals, as well as the outputs of up to twelve analog modules. The functions of the mainframe chassis are limited to providing power, configuration data, and interconnections among the analog modules, as well as physical support. Configuration data is loaded into

Figure 2: EARP-1 logical organization.

EARP-1 in a bit-serial manner. Each analog module contains a shift register for receiving and holding configuration data, and these individual registers are concatenated by the mainframe chassis. This architecture forces the mainframe chassis to be populated consecutively starting from analog module #1 because an empty module slot will prevent any modules in successive slots from receiving data.

Figure 3: EARP-1 mainframe & power supply.

Figure 4: State variable module block diagram.

Figure 5: State variable PWB.

Figure 6: Prototyping PWB.

Figure 7: Serial data format & timing.