All of the below steps were done in the INTEL lab or in the main lab in FAB. You CANNOT telnet into the network from off campus and get this to work.

You can, however, download your own personal copy of the Verilogger Extreme compiler. You go to this link here and choose Verilogger Extreme and the platform of your system. And also fill out your information and click the download button. You will get an email with download link info included. When you click the link you can download software. After you installed the s/w on your computer you can run the test tutorial (adder) right away.

You might get an email regarding the license issue however you can ignore it. You don't need full package of this s/w for this class/term, so you don't need to buy a license.

There are two files you will need for this tutorial:

1. adder.v
2. test_adder.v

Once you log into the network, you will see a folder for SynaptiCad on the desktop. Open the folder and double click on the Verilogger Extreme icon. (You can right click, then copy, then paste this icon on your desktop so it will be there the next time.)

Double clicking on the VeriLogger Extreme icon starts the Verilog simulator. (Click on "OK" to remove the block in the middle of the GUI.)

The first thing you must do is create a "project". Click on Project and then click on New Project. A window will appear where you can type in a project name. For this tutorial, let's call it MY_PROJ. Then click finish. (If you have already created a project, simply click on Project and then Open Project.)

You now need to add all of your source files. Click Project then Add User Source Files. A window will appear. Insert the floppy with the two files (adder.v and test.v) and select them by clicking Open. (Now would be a good time to save your project.)

NOTE: When you save your project, always use "SAVE PROJECT AS" instead of "SAVE PROJECT". You can still use the same name. This will make sure your changes actually get saved!

Build your project by pressing the F7 key. If your program has errors, they will be listed in the lower right quadrant. Otherwise, the variables you define in the test.v file will appear on the timing diagram in the lower left quadrant.

Run your project by pressing the F5 key. This will produce the timing diagram.

To print your timing diagram you can use the standard method of clicking on the printer icon (i.e., the standard way any file is printed under Windows). Alternatively, you can do the following:

• click on File
• click on Print Diagram

• in the "Print or Create Image File" there is a window labeled "Print to:". Select File. Pick a file name of myfile.ps Make sure the file extension is "ps" and NOT "prn". Be sure you record the directory where the file will be stored.
• click on Print.

If you are using the Unix system you can print myfile.ps using the Unix "lpr" command. If you are on the PC network under windows, you will have to use Ghostview to print the file. To do this you must follow the menu path

Click on GS View 4.0 and then open myfile.ps. You can then print the file on any network printer using the same method as is done with any other windows application.