ECE 351

Homework #1 solution

Homework #2

Homework #3 (The testbench is here.)

Homework #4

Homework #5

Homework #6

Quiz #1 solution

Quiz #2 solution

Quiz #3 solution

Quiz #4 solution

Quiz #5 solution

Quiz #6 solution

Quiz #7 solution

Supplemental Material

RTL guidelines

ASIC primer

ASIC and ASSP definitions

RTL definition

FPGA overview

Intro to scripts

synthesis scripts

Parity generator IP datasheet.

Decoder IP datasheet

Lattice Semiconducter coding hints

Xilinx If-vs-Case coding

RTL closure

Spartan-6 datasheet

FPGA programming notes

1. FPGA programming via JTAG (pages 1-6, 12)
2. FPGA via SPI (pages 1-7)
3. JTAG download cable
4. JTAG download cable schematic
5. Synplify_users_guide is here
6. FPGA programming via parallel EPROM
7. JTAG download cable note
8. JTAG architecture
9. FPGA design flow
10. SPI programming schematic
11. The Mentor Graphics Videos are here
12. SystemVerilog interfaces

EDA tools

The Verilog compiler/simulator tutorial is here . You can add signals to the simulator timing diagram by following this procedure.

Using the FPGA synthesizer.

TA INFO: The TA for this class Haera Chung. Her office hours are 1230-1400 in FAB 100 on Tuesdays.