This is the second term of an approved two term undergraduate and graduate sequence. The second term's goals are to continue the study of CMOS circuit and logic design. A laboratory is integrated into the lecture and students will gain skills in device and small scale integrated circuit simulation, and CMOS IC layout.

A topic will be displayed by selecting the at the left of its label and closed by selecting when it is displayed.

Contact Information

Course Outcomes and Syllabus

Logisitcs

Assignments

Notes

Laboratories

Laboratory Assignments

Laboratory assignments are listed in order. Due dates are in each file.

Laboratory 1

Laboratory 2

Laboratory 2

Laboratory 1

P1 (20 points) - Cell description, Cell Symbol, Cell Truth Table, Cell Schematic diagram

P2 (50 points) - Performance analysis of D-latch

P3 (20 points) - Layout

In Section P1, each of Cell Description, Cell Symbol, Cell Truth Table and Cell Schematic diagram is worth 5 points. Points were deducted for following kinds of errors: Schematic is not in publicat ion format, truth table is incorrect, incorrect symbol etc.

In Section P2, each of Q (only) rise and fall, propagation tables for DIN to Q ( only), CK to Q (only), Propagation Delay Equations and Table of latch setup and latch hold times is worth 10 points. Points were deducted for following kinds of errors: Missing or incorrect data/ta ble, missing or incorrect latch setup and hold times.

In Section P3, Layout and LVS report are worth 10 point each. Points were deducted for missing layout or LVS; in LVS report, netlist failed to
match layout; layout does not show layers/pins.

Corners and Tutorials

You will need to collect the ZIP file Corner models." and the new tutorial for http://ece.pdx.edu/~daasch/course/x26/tutorials/Tutorial-switch_simula tor.pdf "Verilog switch level Simulation."

The IC Design and Test Laboratory has release version 1 of a set of place and route tutorials for the Cadence Silicon Ensemble. The tutorials are based on the NCSU CDK.
"Introduction,"
Cadence Setup,

Startup Files

Version 2. of the tutorials have made changes in the generation of the LEF file.
Tutorial 1 Version 2,
Tutorial 2 Version 2,
Tutorial 3 Version 2,
Tutorial 4 Version 2,
Tutorial 5 Version 2.

BitGen

NCSU Bitgen is up and can create Verilog stimulus files for a single bus. Updates could expand the coverage.

Start Up File IC 5.0" for the Version 1.2 and Cadence IC 5.0.

Save this file to your local directory. Use the following UNIX command in the window before you run the Cadence Front to Back Integrated Circuit Design Environment command.

% source startup.txt
% icfb &

Other WWW URLs about IC design and CAD