Adjunct
Research Associate Professor
Department of Electrical and Computer Engineering
IC Design and Test Laboratory
Portland State University
P.O. Box 751
Portland, OR 97207-0751
Office: FAB 40-19
Mobile: (503) 799 6452
Email: cgshirl@cecs.pdx.edu
PhD in Physics, Arizona State University, Tempe, AZ (1974)
M.Sc. in
Physics, University of Melbourne, Australia (1970)
Dr. Shirley worked as a post-doctoral fellow at Carnegie Mellon University, and at U.S. Steel's research laboratories. In 1977 he joined Motorola's Semiconductor R&D Labs in Phoenix, Arizona. Dr. Shirley joined Intel in May 1984, starting in Assembly Technology Development Q&R where he worked on package reliability fundamentals, including assembly test chips and moisture reliability. In 1989 he transferred to TD Q&R in Oregon where he continued to work on moisture reliability of silicon, accelerated moisture test hardware (HAST), and industry standards. He also led the development of Intel’s burn-in methodology. In 1995 he founded Sort-Test TD Q&R, which focused on Q&R Test Methodologies, HVM Optimization etc. In 2004 he founded a Q&R modeling group, and in 2005 he joined Intel’s Corporate Quality Network staff where he was responsible, as Intel’s Q&R Systems Architect and co-manager, for development of Intel’s quality systems. He retired from Intel in 2007, and in 2008 joined the Department of Electrical and Computer Engineering at Portland State University as an Adjunct Research Associate Professor in the Integrated Circuits Design and Test Laboratory.