EE431/531 Microwave Circuit Design I: Lab 2
© B. Pejcinovic, P. Wong, O. Woywode

Introduction

This lab concentrates on the principles of designing impedance matching networks using Smith charts and CAD tools. You will implement both ell and microstrip circuits to match a given load to a specific line impedance. In addition, you will gain experience with MDS techniques such as subcircuits, parameter sweeps, and optimization.

Although impedance matching networks may seem mundane, their proper design and implementation is critical to the efficient transfer of power along the signal path of an amplifier. If there is an impedance mismatch, electrical signals will undergo reflections at the boundary of the impedance discontinuity, which can cause a significant power loss.

Design Specifications

Block diagram

Figure 1: Block diagram of the matching network

Figure 1 shows the basic layout of the circuit you are to design. There is a load impedance ZL that is to be matched to a line with characteristic impedance Z0. The large block in the center of the figure will be replaced by your matching network (either ell or microstrip).

The initial values are Z0 = 50 ohm, ZL = 15 - j5 ohm, and the design frequency is f = 1 GHz.

From the equation Gamma = (z - 1) / (z + 1), where z = Z / Z0 , the reflection coefficient of the load is Gamma_L = 0.5423 | -167.5 degrees.

In the actual circuit, the 50 ohm line is represented by an S-port with a port impedance of R = 50 OH. The 15 - j5 ohm load impedance is approximated by using a 15 ohm resistor and a 31.83 pF capacitor (which has a reactance of approximately -j5 ohm at 1 GHz).

You may be wondering what happens at frequencies other than the design value of 1 GHz. Of course, the capacitor's reactance will change as the frequency changes, so your matching network is unlikely to maintain a perfect impedance match at off-frequencies. However, this is not as unrealistic as you may think, because real transistor amplifiers have S-parameters that can vary widely with frequency, which greatly affects the performance of an attached impedance matching network.

Subcircuits and Miscellaneous Notes

Subcircuit procedure

For simple circuits with few components, it is often best to construct the entire schematic on a single circuit page. As the schematic grows larger in size and complexity, it is more efficient to divide the single circuit into a set of smaller, modular subcircuits that are reusable. Each subcircuit can then be tested individually before being assembled into a master circuit.

The process of creating and using subcircuits is quite easy in MDS. A subcircuit is constructed in almost exactly the same manner as a standard circuit, except for a few additional details:

  1. Construct the subcircuit on a new circuit page.
  2. Identify and mark the input and output terminals of the subcircuit.
  3. Create a symbol for the subcircuit. (Every circuit page has an associated symbol page, which defines the on-screen symbol that MDS uses to represent the subcircuit. Although a standard circuit also has a symbol page, the symbol is usually not defined. Subcircuits, however, require the symbol to be defined explicitly.)
  4. Repeat steps 1 through 3 for each subcircuit.
  5. Construct the master circuit on a new circuit page. Insert the symbol for each subcircuit into its appropriate position within the master circuit.

You will implement your matching networks (both ell and microstrip) as subcircuits. The master circuit consists of S-ports and the load impedance.

Although the circuits for this lab assignment could easily be built on a single circuit page, you are asked to use the subcircuit method for practice.

Miscellaneous Notes

The notation developed in Lab 1 is used extensively here. Refer to the Lab 1 handout for more information.


Ell Matching Networks


Assignment

You are to design two different ell circuits (i.e., inductors and capacitors in an "ell" configuration) to match the 15 - j5 ohm load to the 50 ohm line at an operating frequency of 1 GHz. You have to test both ell matching networks to examine their performance at various frequencies.

You may use any combination of inductors and capacitors that will produce a valid impedance match between the line and the load. The simplest design method is to use ZY-Smith chart paper for your initial computations. Since you will turn in your design charts, carefully annotate them with pertinent information.

Subcircuit construction

Ell subcircuit

Figure 2: An ell matching network configured as a subcircuit

Symbol page

Figure 3: The subcircuit's associated symbol page

"No load" test case


The load impedance is initially omitted and replaced by an S-port for S[2,2] measurements. You can then observe what the load would "see" as the impedance at the output node of the matching network.

Test circuit construction

Figure 4: Master circuit for testing the ell matching network subcircuit with no load impedance

Simulation

Output

Results to turn in

Note: Remember, you need to repeat the same construction, simulation, and output procedures for your second ell matching network. It is highly recommended that you give the second matching network its own, separate test circuit. Just follow this procedure:

Close the 'Test_No_Load1: CIRCUIT PAGE 1' window
. In the ELL workbench, select the Test_No_Load1 circuit icon. Choose [MB:COPY/AS GROUP]. Click and drag the selected icon to another part of the workbench window to create a copy of the original test circuit. Rename the copied icon to Test_No_Load2. You can now open and edit the copied test circuit to use the second matching network. Change the dataset name to DS_Test_No_Load2 before running the simulation. You can also copy the original display page and edit it to use the new dataset name.


"With load" test case


For this case, the load impedance is placed at the output of the matching network. Only one S-port is used in the simulation. You will track S[1,1] to verify the effectiveness of your matching networks.

Test circuit construction

With load master test circuit

Figure 5: Master circuit for testing the ell matching network subcircuit with a load impedance

Simulation

Output

Results to turn in

Note: Remember, you need to repeat the same construction, simulation, and output procedures for your second ell matching network.


Microstrip Matching Networks - Part I


Assignment

You are to design a microstrip circuit to match the 15 - j5 ohm load to the 50 ohm line at an operating frequency of 1 GHz. For the given load impedance, use balanced open-circuited stubs and a series transmission line.

The substrate is Duroid, with a relative permittivity of 2.23 and a height h of 0.7874 mm. You may assume that the microstrip has zero effective thickness.

Use standard Smith chart paper for your initial computations. Since you will turn in your design chart, carefully label it to show how you derived your microstrip values. For consistency, you should express your physical line lengths in either millimeters or centimeters.

You need to manually compute the microstrip line width for a 50 ohm characteristic impedance with a Duroid substrate. Later on you can use the built-in MDS microstrip calculator to confirm your work.

Subcircuit construction

Microstrip subcircuit

Figure 6: A microstrip matching network set up as a subcircuit

LineCalc window

Screen Capture 1: LineCalc dialog window

Test circuit construction


"No optimization" case


You will test the effectiveness of your original microstrip design prior to optimization.

Simulation

Output

Results to turn in


"Parameter sweep" case


You will instruct MDS to sweep the length L of the transmission line microstrip component to see if the impedance match can be improved. The lengths of the open-circuited stubs will be left alone for now.

The subcircuit and master test circuit are unchanged from the "No optimization" case, so you can re-use them. On the other hand, you have to make some minor alterations to the simulation setup for a parameter sweep. If you want to preserve the setup of the original master test circuit, make a copy of the test circuit first. You can then work on the copy without disturbing the original test circuit.

Simulation

Parameter sweep dialog

Screen Capture 2: Parameter sweep setup

Output

Results to turn in


"Full optimization" case


As you may have noticed, parameter sweeps are a powerful but tedious method for performing circuit optimizations. In this section of the lab, you will let MDS do almost all the work to fully optimize your microstrip matching network.

You need to make some fairly radical changes to the simulation setup for an optimization run, and you also have to edit the subcircuit. If you want to preserve your original work, make copies of both the subcircuit and master test circuit first.

Subcircuit changes

Special optimization format

Figure 7: Editing the parameter value for optimization

Simulation

Screen Capture 3: Optimization setup

Goal editor

Screen Capture 4: Goal editor

Output

Results to turn in


Microstrip Matching Networks - Part II


Assignment

Design a new microstrip circuit to match the 15 - j5 ohm load to the 50 ohm line at an operating frequency of 1 GHz. This time, use a quarter-wave transformer and either 1) balanced open-circuited shunt stubs of length 3*Lambda/8, or 2) balanced short-circuited shunt stubs of length Lambda/8. Assume the substrate is Duroid, with the same parameter values as in Part I.

Choose one of the stub configurations and compute the physical microstrip line widths and lengths. This would be a good opportunity to use the MDS microstrip calculator to simplify your work. Just be sure that the MDS calculator is using the correct substrate values.

This is a paper design only. You do not have to construct and simulate your design using MDS, although you are certainly invited to do so if you want to experimentally verify your calculations.

Results to turn in