Visual Software - SYNTHA
A System for Logic Synthesis of Finite State Machines
(contains ESPRESSO)
Abstract
The input is an FSM specification using an autogram, a KISS table or (in
the future) VHDL. The output is an encoded, minimized, and mapped netlist
of gates, which implements the given FSM. A variety of options allow the
user to select encoding strategies and flip-flop types.
Download
the latest version of SYNTHA (08)
Download
MCNC91 FSM Benchmarks
Back to Visual
Software Homepage
This webpage is supported by Alan Mishchenko.