Selected Presentation

• Input Variable Symmetries and Output Equivalences in Combinational Logic (SCL, Intel, Hillsboro, OR; November 13, 2001)
• Boolean Decomposition and Network Optimization (Get2Chip.com, San Jose CA; November 2, 2001)
• Specialized Applications of Decision Diagrams (UC Berkeley, Berkeley CA; October 22, 2001)
• Board Level Routing Problem using SAT (LDL, Portland OR; August 29, 2001)
• Universally Testable AND-EXOR Networks (LIRRM, Montpellier, France; February 26, 2001)
• Zero-Suppressed Binary Decision Diagrams and Their Applications in Logic Synthesis (LIRRM, Montpellier, France; February 23, 2001)
• Overview of Research in Logic Synthesis and Optimization (LIRRM, Montpellier, France; February 22, 2001)
• Towards SPFD-Based Technology Mapping (SCL, Intel, Hillsboro, OR; October 17, 2000)
• An Algorithm for Bi-Decomposition of Logic Functions (SCL, Intel, Hillsboro, OR; September 26, 2000)
• Multi-Fault-Model ATPG for Binary and Multi-Valued Circuits (Mentor Graphics, Wilsonville OR, March 10, 2000)
• Implicit Algorithms for Input Support Minimization of Multi-Valued Relations (ECE PSU, Portland OR; February 24, 2000)
• A New Approach to Structural Analysis and Transformation of Networks (ECE PSU, Portland OR; November 29, 1999)
• Applications of Binary Decision Diagrams in Logic Synthesis, Verification, and Testing (UMass, Amherst MA, October 22, 1999)