43. X. Song, W. N. N. Hung, A. Mishchenko, M. Chrzanowska-Jeske, A. Coppola, and A. Kennings, Board-level multiterminal net assignment for the partial cross-bar architecture, IEEE Transactions on VLSI Systems, June 2003, Vol. 11 (3), pp. 511-514.
42. A. Mishchenko and R. K. Brayton. A Theory of Non-Deterministic Networks. Proc. of ICCAD 2003, San Jose, Nov. 9 -13, 2003.
41. A. Mishchenko. Fast Computation of Symmetries in Boolean Functions. Accepted to IEEE Transactions on CAD.
40. A. Mishchenko and T. Sasao. Large-Scale SOP Minimization Using Decomposition and Functional Properties. Proc. Design Automation Conference 2003.
39. A. Mishchenko, X. Wang, T. Kam. A New Enhanced Constructive Decomposition and Mapping Algorithm. Proc. Design Automation Conference 2003.
38. S. Nagayama, A. Mishchenko, T. Sasao, J. Butler. Minimization of Average Path Length in BDDs by Variable Reordering. Proc. of International Workshop on Logic and Synthesis 2003, Los Angeles, May 28-30, 2003.
37. A. Mishchenko, R. K. Brayton, T. Sasao. Exploring Multi-Valued Minimization Using Binary Methods. Proc. of International Workshop on Logic and Synthesis 2003, Los Angeles, May 28-30, 2003.
36. A. Mishchenko and R. K. Brayton. A Theory of Non-Deterministic Networks. Proc. of International Workshop on Logic and Synthesis 2003, Los Angeles, May 28-30, 2003.
35. M. Perkowski and A. Mishchenko. Logic Synthesis for Regular Layout using Satisfiability. 5th Intl. Workshop on Boolean Problems, September 2002, Freiberg, Germany.
34. A. Mishchenko, R. K. Brayton. A Theory of Non-Deterministic Networks. 5th Intl. Workshop on Boolean Problems, September 2002, Freiberg, Germany.
33. J.-H. Jiang, A. Mishchenko, R. Brayton. Reducing Multi-Valued Algebraic Operations to Binary. Proc. DATE 2003.
32. A. Mishchenko and R. K. Brayton. Simplification of Non-Deterministic Multi-Valued Networks. International Conference on Computer Aided Design, November 10-14, 2002, San Jose, CA.
31. A. Mishchenko and M. Perkowski. Logic Synthesis of Reversible Wave Cascades. Proc. of International Workshop on Logic and Synthesis 2002, New Orleans, Louisiana, June 4-7, 2002.
30. A. Mishchenko and T. Sasao. Encoding of Boolean Functions and Its Application to LUT Cascade Synthesis. Proc. of International Workshop on Logic and Synthesis 2002, New Orleans, Louisiana, June 4-7, 2002.
29. J.-H. Jiang, A. Mishchenko, R. Brayton. Reducing Multi-Valued Algebraic Operations to Binary. Proc. of International Workshop on Logic and Synthesis 2002, New Orleans, Louisiana, June 4-7, 2002.
28. S. Sinha, A. Mishchenko, R. Brayton. Topologically Constrained Logic Synthesis. Proc. of International Workshop on Logic and Synthesis 2002, New Orleans, Louisiana, June 4-7, 2002.
27. A. Mishchenko and R. K. Brayton. Simplification of Non-Deterministic Multi-Valued Networks. Proc. of International Workshop on Logic and Synthesis 2002, New Orleans, Louisiana, June 4-7, 2002.
26. A. Mishchenko and R. K. Brayton. A Boolean Paradigm in Multi-Valued Logic Synthesis. Proc. of International Workshop on Logic and Synthesis 2002, New Orleans, Louisiana, June 4-7, 2002.
25. M. Gao, J.-H. Jiang, Y. Jiang, Y. Li, A. Mishchenko, S. Sinha and R. Brayton. Optimization of Multi-Valued Multi-Level Networks. Invited presentation at The 32d International Symposium on Multi-Valued Logic, May 15-18, 2002. Boston, MA.
24. X. Song, W. N. N. Hung, A. Mishchenko, M. Chrzanowska-Jeske, A. Coppola, and A. Kennings. Board-Level Multiterminal Net Assignment. Proc. of 12th Great Lakes Symposium on VLSI, April 2002, Binghamton, NY.
23. B. Steinbach and A. Mishchenko. A New Approach to Exact ESOP Minimization. Proc. of Reed-Muller Workshop, August 2001, Starkville, Mississippi, pp. 66-81.
22. A. Mishchenko and M. Perkowski. Fast Heuristic Minimization of Exclusive Sum-of-Products. Proc. of Reed-Muller Workshop, 2001, Starkville, Mississippi, pp. 242-250.
21. M. Perkowski and Portland Quantum Logic Group. A General Decomposition for Reversible Logic. Proc. of Reed-Muller Workshop, 2001, Starkville, Mississippi, pp. 119-138.
20. M. Perkowski and Portland Quantum Logic Group. Regularity and Symmetry as a Base for Efficient Realization of Reversible Logic Circuits. Proc. of International Workshop on Logic and Synthesis, June 2001, Lake Tahoe, California.
19. J. Jacob and A. Mishchenko. Unate Decomposition of Boolean Functions. Proc. of International Workshop on Logic and Synthesis, June 2001, Lake Tahoe, California.
18. A. Mishchenko, B. Steinbach, M. Perkowski. Bi-Decomposition of Multi-Valued Relations. Proc. of International Workshop on Logic and Synthesis, June 2001, Lake Tahoe, California.
17. A. Mishchenko, B. Steinbach, M. Perkowski. An Algorithm for Bi-Decomposition of Logic Functions. Proc. of DAC 2001, June 18-22, Las Vegas, pp. 103-108.
16. M. Chrzanowska-Jeske, A. Mishchenko. Kronecker Lattice Diagrams: Merging Logic Synthesis with Regular Layout. To be submitted.
15. A. Mishchenko. Implicit Representation of Discrete Objects. Proc. of 3d Oregon Symposium on Logic, Design,and Learning (LDL '00), May 22 2000, Porland, Oregon.
14. M. Chrzanowska-Jeske, A Mishchenko, M. Perkowski. New Families of Canonical Reed-Muller Expansions. Accepted to VLSI Design, May 2000.
13. A. Mishchenko, C. Files, M. Perkowski, B. Steinbach, Ch. Dorotska. Implicit Algorithms for Multi-Valued Input Support Manipulation. Proc. of 4th Intl. Workshop on Boolean Problems, September 2000, Freiberg, Germany.
12. A. Mishchenko. An Efficient Implementation of L Language Data Processing Algorithms. Proc. of 2d International Conference UKRPROG '00 (May 23-26, 2000), Kiev, Ukraine. Published in the special issue of the journal Problemy programirovaniya (Problems in Programming), #1-2, 2000, pp. 335-344.
11. N. Venkataramaiah, K. Dill, D. Hall, M. A. Perkowski, A. Mishchenko, U. Kalay. Highly Testable Finite State Machines Based on Exor Logic. 7th IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM '99), Victoria, B.C., Canada, August 23-25, 1999, pp. 440-443.
10. M. Chrzanowska-Jeske, A Mishchenko, M. Perkowski. A Family of Canonical AND/EXOR Forms that Includes Exact Minimum ESOPs. 4th International Workshop on Applications of the Reed-Müller Expansion in Circuit Design (Reed-Müller 99), University of Victoria, Victoria B.C., Canada, August 20-21, 1999, pp. 1-15.
9. A. A. Mishchenko and M. A. Perkowski. TRACE: A Visual Software System to Explore Properties of Reed-Muller Movement Functions. 4th International Workshop on Applications of the Reed-Müller Expansion in Circuit Design (Reed-Müller 99), University of Victoria, Victoria B.C., Canada, August 20-21, 1999, pp. 265-271.
8. M. A. Perkowski, A. N. Chebotarev, A. A. Mishchenko. Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints. The First NASA/DOD Workshop on Evolvable Hardware (NASA/DOD-EH 99). Jet Propulsion Laboratory, Pasadena, California, USA, July 19-21, 1999, pp. 129-138. How to format papers.
7. M. Perkowski, R. Malvi, S. Grygiel, M. Burns, and A. Mishchenko. Graph Coloring Algorithms for Fast Evaluation of Curtis Decompositions. The 36th ACM/IEEE Design Automation Conference (DAC 99). New Orleans, LA, USA, June 21-25, 1999, pp. 125-130. PowerPoint presentation University booth poster
The following four papers are originally published in Russian in Kiev in the journal Kibernetika i Sistemny Analiz, later translated into English and published by Plenum Publishing Company Inc. (Journal Customer Services, 233 Spring Street, New York, NY 10013-1578, Tel 212-620-8468, Fax 212-807-1047).
6. A. A. Mishchenko, A. T. Mishchenko. Formalization of logic design of the register components in discrete systems. Cybernetics and System Analysis. 1997, N2, pp. 32-44.
5. A. A. Mishchenko. A CAD system for automated synthesis of controlling automata. Cybernetics and System Analysis. 1997, N3, pp. 23-30.
4. A. A. Mishchenko. On properties of reversible polynomial functions. Cybernetics and System Analysis. 1997, N4, pp. 44-49.
3. Yu. V. Kapitonova, T. P. Marianovich, A. A. Mishchenko. On logic design and simulation of computer system components. Cybernetics and System Analysis. 1997, N6, pp. 25-41.
The remaining two papers are published in Ukrainian:
2. A. A. Mishchenko, N. M. Mishchenko. TEMP: A universal evolving language processor. UKRSOFT-95: V Ukrainian Language Software Scientific and Practical Conference. Lviv, 1995.
1. A. A. Mishchenko, N. M. Mishchenko. Automated generation of dictionaries of false homonyms of flections in Ukrainian language. UKRSOFT-94: IV Ukrainian Language Software Scientific and Practical Conference. Lviv, 1994.