Advanced Computer Architecture I

Instructor: Alaa R. Alameldeen

Spring 2009: MW 6:40-8:30 PM, URBN 204 (Note Room Change)

What's New?

• 14-Jun: All Grades (including final and project) posted.
• 1-Jun: Project submission instructions posted.
• 31-May: Grades except final and project posted.
• 31-May: Fall 2008 Final posted.
• 15-Apr: Project Guidelines and Potential Topics posted.
• 26-Mar: Class description notes posted
• 18-Mar: Tentative class schedule posted

Class Information

• Date and Time: Mondays and Wednesdays 6:40 PM - 8:30 PM
• Place: URBN 303 URBN 204 (Note Room Change)
• Office Hours: By appointment
• Class description: slides , six-per-page

Tentative Class Schedule

Homeworks and Projects

• Review Guidelines: Paper review guidelines and submission instructions.
• Homework 1: Due Apr 6.
• Homework 2: Due Apr 22.
• Homework 2 Solutions .
• Guidelines on running long simulation jobs
• Project Guidelines and Potential Topics

Exams and Grades

• Sample midterm exam from Fall 2008: Midterm and solution key
• Midterm exam: Exam and solution key
• Sample final exam from Fall 2008: Final
• Midterm grades
• All grades (except final and project)

Reading List

(Please Respect the IEEE and ACM Copyrights)

Note: This is an initial list that may change later. Do not print all papers just yet.

• David A. Patterson and Carlo H. Sequin, "RISC I: A Reduced Instruction Set VLSI Computer," ISCA 1981.
• James E. Smith and Gurindar S. Sohi, "The Microarchitecture of Superscalar Processors," Proc. IEEE, 1995.
• Doug Burger and Todd M. Austin, "The SimpleScalar Tool Set, Version 2.0," Technical Report #1342, University of Wisconsin-Madison, 1997.
• Todd M. Austin, "A User's and Hacker's Guide to the SimpleScalar Architectural Research Tool Set," Tutorial, 1997.
• Tse-Yu Yeh and Yale N. Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction," ISCA 1992.
• Scott McFarling, "Combining Branch Predictors," WRL Technical Note, 1993.
• Eric Rotenberg, Steve Bennet, and James E. Smith, "Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching," MICRO 1996.
• Daniel A. Jimenez and Calvin Lin, "Dynamic Branch Prediction with Perceptrons," HPCA 2001.
• James E. Smith and Andrew R. Pleszkun, "Implementing Precise Interrupts in Pipelined Processors," IEEE Transactions on Computers, 1988.
• Gurindar S. Sohi and Sriram Vajapeyam, "Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors," ISCA 1987.
• George Z. Chrysos and Joel S. Emer, "Memory Dependence Prediction Using Store Sets," ISCA 1998.
• David Kroft, "Lockup-Free Instruction Fetch/Prefetch Cache Organization," ISCA 1981.
• Mark D. Hill and Alan Jay Smith, "Evaluating Associativty in CPU Caches," IEEE Transactions on Computers, 1989.
• Norman P. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers," ISCA 1990.
• Tien-Fu Chen and Jean-Loup Baer, "Effective Hardware-Based Data Prefetching for High-Performance Processors," IEEE Transactions on Computers, 1995.
• Simcha Gochman et al., "The Intel Pentium M Processor: Microarchitecture and Performance," Intel Technology Journal 2003.
• David B. Papworth, "Tuning the Pentium Pro Microarchitecture," IEEE Micro 1996.
• Joseph A. Fisher, "Very Long Instruction Word Architectures and the ELI-512," ISCA 1983.
• Harsh Sharangpani, "Itanium Processor Microarchitecture," IEEE Micro 2000.
• Dean M. Tullsen, Susan J. Eggers and Henry M. Levy, "Simultaneous Multithreading: Maximizing On-Chip Parallelism," ISCA 1995.
• Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo and Rebecca L. Stamm, "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor ," ISCA 1996.
• Gurindar S. Sohi, Scott E. Breach, and T.N. Vijaykumar, "Multiscalar Processors," ISCA 1996.
• Amir Roth and Gurindar S. Sohi, "Speculative Data-Driven Multithreading," HPCA 2001.
• Avinash Sodani and Gurindar S. Sohi, "Dynamic Instruction Reuse," ISCA 1997.
• Onur Mutlu et al., "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors," HPCA 2003.
• Srikanth T. Srinivasan et al., "Continual Flow Pipelines," ASPLOS 2004.
• Mikko H. Lipasti and John Paul Shen, "Exceeding the Dataflow limit via Value Prediction," MICRO 1996.
• Yiannakis Sazeides and James E. Smith, "The Predictability of Data Values," MICRO 1997.
• Changkyu Kim, Doug Burger and Stephen W. Keckler, "An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches," ASPLOS 2002.

Useful Links

• Previous ECE 587/687 offering, Fall 2008
• Previous ECE 587/687 offering from Dr. Haitham Akkary, Fall 2007
• WWW Computer Architecture Webpage
• Scientific Method
• Writer's Handbook: Writing guidelines from the University of Wisconsin-Madison's Writing Center.
• Oral Presentation Advice from Prof. Mark Hill