Advanced Computer Architecture I

Instructor: Alaa R. Alameldeen

Spring 2012: Tuesdays and Thursdays 7:00-8:50 PM, Willow Creek Center 312

What's New?

• 17-Apr: Project guidelines and potential ideas posted
• 28-Mar: Tentative class schedule posted

Class Information

• Date and Time: Tuesdays and Thursdays 7:00 PM - 8:50 PM
• Place: WCC 312
• Office Hours: Tuesdays and Thursdays, after class
• TA: Yafei Yang (Email: yafei AT cecs dot pdx dot edu, Office hours Wed 5-6 PM in FAB 60-12)
• Class description: slides , six-per-page

Tentative Class Schedule

Week	Day	Date	Topic	Readings (before class)	Homework/Project	Class Notes
1	Tue	3-Apr	Introduction, superscalar processors overview		HW1 Out	slides , six-per-page
1	Thu	5-Apr	Superscalar Processors Microarchitecture	Smith & Sohi, Proc. IEEE 1995 (Review)		slides , six-per-page
2	Tue	10-Apr	Branch Prediction	Yeh & Patt, ISCA 1992 (Review) McFarling, Tech Report, 1993 (Read)	HW1 Due	slides , six-per-page
2	Thu	12-Apr	Simplescalar	Simulator Documents (Technical Report, Tutorial)	HW2 Out	slides , six-per-page
3	Tue	17-Apr	Trace Cache	Rotenberg et al., Micro 1996 (Review) Jimenez & Lin, HPCA 2001 (Skim)		slides , six-per-page
3	Thu	19-Apr	Precise Interrupts	Smith & Pleszkun, TOC 1988 (Review)		slides , six-per-page
4	Tue	24-Apr	Issue Logic	Sohi & Vajapeyam, ISCA 1987 (Review) Palacharla et al., ISCA 1997 (Read)	Project Proposals Due	slides , six-per-page
4	Thu	26-Apr	Memory Ordering	Chrysos & Emer, ISCA 1998 (Review)	HW2 Due	slides , six-per-page
5	Tue	1-May	Caches	Kroft, ISCA 1981 (Read) Hill & Smith, IEEE TOC, 1989 (Skim)		slides , six-per-page
5	Thu	3-May	Prefetching	Jouppi, ISCA 1990 (Review) Chen & Baer, IEEE TOC 1995 (Skim)		slides , six-per-page
6	Tue	8-May	Midterm Exam	In class at 7 PM - 90 minutes		Open Notes
6	Thu	10-May	Pentium Pro and Pentium M Architectures	Gochman et al., Intel TJ 2003 (Review) Papworth, IEEE Micro 1996 (Skim)		Pentium Pro Slides from Dr. Akkary Online Pentium M slides
7	Tue	15-May	VLIW + Itanium Architecture	Fisher, ISCA 1983 (Review) Sharangpani, IEEE Micro 2000 (Skim)		slides , six-per-page , Online Itanium Slides
7	Thu	17-May	Simultaneous Multithreading	Tullsen et al., ISCA 1995 (Review) Tullsen et al., ISCA 1996 (Skim)		slides , six-per-page
8	Tue	22-May	Multiscalar and Speculative Multithreading	Sohi et al., ISCA 1996 (Review) Roth & Sohi, HPCA 2001 (Skim)	Project Progress Report Due	Prof. Sohi's Multiscalar Slides
8	Thu	24-May	Value Prediction	Sazeides & Smith, Micro 1997 (Read) Lipasti & Shen, MICRO 1996 (Skim)		Conference Talk from Multiscalar Webpage
9	Tue	29-May	Runahead Execution and Continual Flow Pipelines	Multu et al., HPCA 2003 (Review), Srinivasan et al., ASPLOS 2004 (Read)		Prof. Multu's Conference Talk Dr. Rajwar's Conference Talk
9	Thu	31-May	Energy-Efficient Design	Chishti, et al., Micro 2009 (Read)		slides , six-per-page
10	Tue	5-Jun	TBD
10	Thu	7-Jun	Project Presentations	6:30-9PM	Project due
10	Fri	8-Jun	Final Exam	7-8:30 PM
12	Wed	20-Jun	No Class		Grades Out

Homeworks and Projects

• Review Guidelines: Paper review guidelines and submission instructions.
• Homework 1: Due Apr 4.
• Homework 2: Due Apr 20.
• Guidelines on running long simulation jobs
• Project submission instructions

Exams and Grades

• Sample midterm exam from Fall 2008: Exam and solution key
• Sample midterm exam from Spring 2009: Exam and solution key
• Sample midterm exam from Spring 2010: Exam and solution key
• Sample final exams: Fall 2008, Spring 2009, Spring 2010

Reading List

(Please Respect the IEEE and ACM Copyrights)

Note: This is an initial list that may change later. Do not print all papers just yet.

• David A. Patterson and Carlo H. Sequin, "RISC I: A Reduced Instruction Set VLSI Computer," ISCA 1981.
• James E. Smith and Gurindar S. Sohi, "The Microarchitecture of Superscalar Processors," Proc. IEEE, 1995.
• Doug Burger and Todd M. Austin, "The SimpleScalar Tool Set, Version 2.0," Technical Report #1342, University of Wisconsin-Madison, 1997.
• Todd M. Austin, "A User's and Hacker's Guide to the SimpleScalar Architectural Research Tool Set," Tutorial, 1997.
• Tse-Yu Yeh and Yale N. Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction," ISCA 1992.
• Scott McFarling, "Combining Branch Predictors," WRL Technical Note, 1993.
• Eric Rotenberg, Steve Bennet, and James E. Smith, "Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching," MICRO 1996.
• Daniel A. Jimenez and Calvin Lin, "Dynamic Branch Prediction with Perceptrons," HPCA 2001.
• James E. Smith and Andrew R. Pleszkun, "Implementing Precise Interrupts in Pipelined Processors," IEEE Transactions on Computers, 1988.
• Gurindar S. Sohi and Sriram Vajapeyam, "Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors," ISCA 1987.
• Subbarao Palacharla, Norman P. Jouppi, and James E. Smith, "Complexity-Effective Superscalar Processors," ISCA 1997.
• George Z. Chrysos and Joel S. Emer, "Memory Dependence Prediction Using Store Sets," ISCA 1998.
• David Kroft, "Lockup-Free Instruction Fetch/Prefetch Cache Organization," ISCA 1981.
• Mark D. Hill and Alan Jay Smith, "Evaluating Associativty in CPU Caches," IEEE Transactions on Computers, 1989.
• Norman P. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers," ISCA 1990.
• Tien-Fu Chen and Jean-Loup Baer, "Effective Hardware-Based Data Prefetching for High-Performance Processors," IEEE Transactions on Computers, 1995.
• Simcha Gochman et al., "The Intel Pentium M Processor: Microarchitecture and Performance," Intel Technology Journal 2003.
• David B. Papworth, "Tuning the Pentium Pro Microarchitecture," IEEE Micro 1996.
• Joseph A. Fisher, "Very Long Instruction Word Architectures and the ELI-512," ISCA 1983.
• Harsh Sharangpani, "Itanium Processor Microarchitecture," IEEE Micro 2000.
• Dean M. Tullsen, Susan J. Eggers and Henry M. Levy, "Simultaneous Multithreading: Maximizing On-Chip Parallelism," ISCA 1995.
• Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo and Rebecca L. Stamm, "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor ," ISCA 1996.
• Gurindar S. Sohi, Scott E. Breach, and T.N. Vijaykumar, "Multiscalar Processors," ISCA 1996.
• Amir Roth and Gurindar S. Sohi, "Speculative Data-Driven Multithreading," HPCA 2001.
• Avinash Sodani and Gurindar S. Sohi, "Dynamic Instruction Reuse," ISCA 1997.
• Onur Mutlu et al., "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors," HPCA 2003.
• Srikanth T. Srinivasan et al., "Continual Flow Pipelines," ASPLOS 2004.
• Mikko H. Lipasti and John Paul Shen, "Exceeding the Dataflow limit via Value Prediction," MICRO 1996.
• Yiannakis Sazeides and James E. Smith, "The Predictability of Data Values," MICRO 1997.
• Changkyu Kim, Doug Burger and Stephen W. Keckler, "An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches," ASPLOS 2002.
• Zeshan Chishti et al., "Improving Cache Lifeime Reliability at Ultra-Low Voltages," Micro 2009.

Useful Links

• Previous ECE 587/687 offering, Fall 2008
• Previous ECE 587/687 offering, Spring 2009
• Previous ECE 587/687 offering, Spring 2010
• Previous ECE 587/687 offering, Spring 2011
• Previous ECE 587/687 offering from Dr. Haitham Akkary, Fall 2007
• WWW Computer Architecture Webpage
• Scientific Method
• Writer's Handbook: Writing guidelines from the University of Wisconsin-Madison's Writing Center.
• Oral Presentation Advice from Prof. Mark Hill