HIGH-LEVEL SYNTHESIS AND DESIGN AUTOMATION.



This class teaches high level synthesis for ASIC and FPGA technology. Embedded Systems and Image Processing/DSP architectures are emphasized. This year, 2008, much new material was added and much old material was removed so please look to the new lectures that will arrive one by one during the class.
  1. Full lectures, exams and homeworks for the class from year 2008. All material was covered.

  2. Full lectures, exams and homeworks for the class from previous year. You can use this as an auxiliary material and for projects.
  3. Literature. Includes mandatory and auxiliary books. More research papers will be added.

    Auxiliary Information for class in previous years.

    Materials given below were used in both this class and formal verification class. Most of the formal verification material is no more taught here, but we use the same VHDL and Verilog and other design examples. Formal methods web-pages are also useful.
    1. Class contents from year 2004. Not all material was covered.
    2. Classs contents for year 1999.
    3. Theoretical foundation of formal methods of system description and design.
    4. Typical homeworks
    5. Classes in Formal Verification and Formal methods in other universities.
    6. Projects for formal verification and design from year 2000.
    7. Digital System Design examples for simulation, synthesis and verification.
    8. Companies, universities and groups that perform research in high level synthesis and verification.
    9. Benchmarks for formal verification.
    10. Commercial Companies that work on formal verification.
    11. Information about programming languages and formal methods, some used in verification.
    12. Formal Verification and Design class contents for year 1999. We use some examples from there.
    13. Formal Verification and Design class contents from year 1998. We use some examples from there.
    14. Materials for Formal Verification and Design class from year 2000. Still used as a source of projects.

    NEW MATERIAL ADDED FOR YEAR 2008



    Here you can find exam material for the second midterm.

    MANDATORY LECTURES ABOUT FPGAS AND FPGA ARCHITECTURES.

    1. Systolic one dimensional architecture examples.
    2. Motivation To FPGA Systems. SORTERS.
    3. FPGAs. Overview.
    4. Altera Corporate Information.
    5. FPGA Logic CAD software.
    6. Design Technologies And CAD.
    7. FPGA logic emulation and reconfigurable systems.
    8. Advanced FPGA chips and systems.
    9. FPGA educational boards and projects.
    10. Design Challenges And Technologies For Embedded Systems.



    ADDITIONAL (NON-MANDATORY) LECTURES ABOUT FPGAS AND FPGA ARCHITECTURES.

    1. FPGA. Additional Lecture.
    2. FPGA. Additional lecture: RECONFIGURABLE high-level.
    3. Additional Lecture: Reconfigurable Systems.
    4. Additional Lecture: FPGAs and ADOBE PLUG Image Processing.

    MANDATORY LECTURES ABOUT OPTIMIZATION METHODS.

    1. SAT introduction.
    2. Branch and bound.
    3. Graph Coloring.
    4. Introduction to Evolutionary Computation.
    5. Evolutionary Algorithms.
    6. Simulated Annealing.
    7. Simulated Annealing And Tabu Search.
    8. Integer Programming And CPLEX.

    ADDITIONAL (non-MANDATORY) LECTURES ABOUT OPTIMIZATION METHODS.

    1. AUXILIARY: 2-graph-coloring-hypergraphs.
    2. AUXILIARY-2007-0003.GeneticProgramming.
    3. AUXILIARY-2007-0005-genetic-logic-synthesis.
    4. AUXILIARY 1 SAT.

    MANDATORY LECTURES ABOUT SCHEDULING, ALLOCATION, BINDING, PARTITIONING, ETC.

    1. High Level Synthesis Overview.
    2. Architectural Design. Exam Problems.
    3. Scheduling, not ILP, not Force Scheduling.
    4. Register allocation using graph coloring.
    5. Scheduling and Allocation, complete example for exam.
    6. Estimations and transformations.
    7. System Partitioning.
    8. Pipelining Methods.
    9. Memory management.
    10. Auxiliary. CAD tools use.